1. Field of the Invention
The invention relates to data converters and, more particularly, to analog-to-digital data converters, multi-bit analog delta-sigma modulators, and feedback processing.
2. Background
Conventional delta-sigma modulators include single bit delta-sigma modulators, multi-bit delta-sigma modulators, continuous time delta-sigma modulators, and discrete-time delta-sigma modulators. Conventional delta-sigma modulators often utilize quantizers and analog and/or digital feedback. A common example of a function implemented in digital feedback circuitry of a multi-bit analog delta-sigma modulator is dynamic element mismatch shaping.
A common problem in the implementation of delta-sigma modulators, such as multi-bit analog delta-sigma modulators, is delay in quantizer and feedback circuitry. Conventional quantizers and feedback loops operate at the same throughput rate as a main path of the delta-sigma modulator. As a result, each process performed by a quantizer and/or feedback loop adds delay to the feedback signal. Delay can degrade stability of the modulator loop and can degrade noise-shaping performance of the modulator loop. This becomes a more difficult problem in a multi-bit, highspeed modulator, especially as more bits are used in the feedback.
In order to reduce delay, conventional delta-sigma modulators utilize quantizers and feedback circuitry with a small number of clock periods of throughput delay. This, however, limits the number of processing steps that can be performed.
In order to increase the number of processing steps, conventional delta-sigma modulators utilize complex clocking schemes that provide separate clock pulses for different events within the quantizer and the feedback circuitry. In these systems, separate clock pulses are generated for different events that occur within the quantizer and the digital feedback circuitry. Succeeding clock pulses with small delays between them may be used to control succeeding events. Separate clock lines are required for each succeeding clock signal and these signals must be synchronized properly. The additional parasitics and the added complexity of accurately synchronizing numerous clock signals with small delays between them can increase the power, area, and the overall design complexity. These drawbacks can become particularly limiting for high clock rates.
What is needed are methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops.